代做Project 7: Sequential Calculator: EECS 270 001 FA 2025代写留学生Matlab程序

EECS 270 001 FA 2025

Project 7: Sequential Calculator

Sequential Calculator

Overview

We are all familiar with the basic four-function calculator which has evolved over the years from the ancient two-function (addition and subtraction) abacus to today's ubiquitous app on our mobile devices (check out this history of the calculator (https://www.thecalculatorsite.com/articles/units/history-of-the-calculator.php) ). The goal of this project is to emulate a four-function calculator on the DE2-115 board. This is essentially an example of Register Transfer Level (RTL) design in which the overall funtionality is fairly simple to state: you perform. a sequence of computations by entering decimal numbers and arithemtic operations on a numeric keypad and observe the results on a numeric display (typically an LCD screen).

Emulating this functionality on the DE2-115 board poses a couple of challeneges.

Unless we connect a keypad to the board (future project!) we have to figure out a way of using the slider switches and push-button keys to enter numbers and operations.

Until we figure out how to use the LCD display (future project!) we must settle for displaying the results on the 7-segment HEX displays.

Preparation

Review the lectures on RTL design (https://umich.instructure.com/courses/778001/pages/session-17-register-transfer-level-rtl-design) and Sequential Multiplication (https://umich.instructure.com/courses/778001/pages/session-19-sequential-multiplication) and use the included Verilog specifications for the Cash Register and Booth Multiplier projects to practice debugging and verifying functional correctness using ModelSim.

Review the included starter and helper Verilog modules.

Design Specification

The calculator performs addition (+), subtraction (-), multiplication (x), and quotient (/) operations on 11-bit two's complement integers (full-fledged division requires introducing floating-point numbers which are beyond the scope of EECS 270!)

I/O Interface

Figure 1 shows the datapth/control decomposition and the DE2-115 interface of the calculator.

Entering and displaying numbers: Signed-magnitude numbers, in the range [-1023, 1023, can be entered using SW[10:0] and should be displayed on {HEX7, HEX6, HEX5, HEX4}. Operation results should be displayed on {HEX3, HEX2, HEX1, HEX0}. Numbers outside the range [-999, 999] should be displayed as - - - - indicating "can't be displayed'.

Entering operations: The four arithmetic operations can be entered by pressing a pushbutton KEY with SW[17] set to 0. Refer to the mapping in Figure1.

Entering commands: Besides entering numbers, two KEYs are used to enter the following commands when SW[17] is set to 1:

= (equals): Pressing KEY[3] displays the result of the operation on {HEX3, HEX2, HEX1, HEX0}.

C (clear): Pressing KEY[0] clears the result display and returns the calculator to its initial state.

Overflow indicator: Overflow should be indicated by LEDG[8] if any operation result is outside the range of 11-bit two's complement numbers, ie., [-1024, 1023] (would have been better if this was a red LED because of its location between the HEX displays!)

The calculator uses the built-in 50MHz CLOCK_50 which may need to be slowed down to eliminate potential timing errors.

Figure 1: Four-Function Calculator Interface and Datapath/Control Decomposition

Module Instantiation Graph

Figure 2 shows the project's module instantiation graph and the templates for the three bolded modules. You are only resposible for implementing these three modules and any other lower-level modules that they instantate. We are providing the remaining six modules which you can instantiate in your own code as indicated by the module instantation graph.

Figure 2: Module Instantiation Graph. You only need to implement the three bolded modules.

The functions performed by these helper modules are as follows:

module Clock_Div (https://umich.instructure.com/courses/778001/files/41464917?wrap=1) (https://umich.instructure.com/courses/778001/files/41464917/download?download_frd=1) : We used this module in the traffic light controller project to generate an approximate 1Hz clock. In this project it is quite likely that your implementation will operate without timing errors at 50MHz. This module is provided in case you need to run at a slightly slower frequency to avoid metastability issues.

module Binary_to_7SEG (https://umich.instructure.com/courses/778001/files/41464919? wrap=1) (https://umich.instructure.com/courses/778001/files/41464919/download? download_frd=1) : This module is a generalization of the B4_to_7SEG module you used in Lab 6. It handles the rendition of signed-magnitude and two's complement numbers on the seven-segment HEX displays.

module SM2TC (https://umich.instructure.com/courses/778001/files/41464987?wrap=1) (https://umich.instructure.com/courses/778001/files/41464987/download?download_frd=1) : This module converts a signed-magnitude number to is two's complement equivalent.

module TC2SM (https://umich.instructure.com/courses/778001/files/41464989?wrap=1) (https://umich.instructure.com/courses/778001/files/41464989/download?download_frd=1) : This module converts a two's complement number to its signed-magnitude equivalent.

module FullAdder (https://umich.instructure.com/courses/778001/files/41464918?wrap=1) (https://umich.instructure.com/courses/778001/files/41464918/download?download_frd=1) : The iconic full adder module!

module AddSub (https://umich.instructure.com/courses/778001/files/41464988?wrap=1) (https://umich.instructure.com/courses/778001/files/41464988/download?download_frd=1) : A parameterized ripple add/subtract module.

You should download these modules and study them to understand what they do and how they do it. In other words, don't just use them as black boxes. You may be asked about them on the final exam!

Operation

Figure 3 shows a typical calculation sequence.

When turned on, the calculator should display 0.

Entering "5 =" displays 5.

Entering any sequence of operations has no effect until another number is entered. In this case entering "7 =" displays 35 corrsponding to 5 7. In other words, The performed operation is the last one selected.

The next displayed result is 30 corresponding to 35 5.

30 / 4 displays the quotient 7.

Entering C displays 0.

Figure 3: Typical Usage Scenario

Calculator Datapath

Designing a complex RTL circuit involves specifying a datapath "architecture" and a corresponding controller. To make this project manageable, you are only asked to design the controller for the datapath shown in Figure 4. The computational core of the datapath is an 11-bit adder/subtractor module which, naturally, performs the calculator's addition and subtraction operations. Using suitable multiplexing, it is also "shared" by the multiplication and quotient units.

Note that if your controller is for a different datapath, e.g., using more than one add/subtract unit, you will lose points.

The Verilog "FourFuncCalc" starter module in Figure 5 (also available as an editable Verilog file (https://umich.instructure.com/courses/778001/files/41464993?wrap=1) (https://umich.instructure.com/courses/778001/files/41464993/download? download_frd=1) ) specifies the various datapath components and is annotated to help you add the missing parts, particularly the controller states and their transitions and the commands issued by the controller to update datapath state.

Figure 4: Four-Function Calculator Datapath