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CS 447 Computer Organization and Assembly Language

Project 3: μMIPS

Released: 23:59 Thursday, April 4th, 2024.

Due: 17:59 Monday, April 22nd, 2024.

Let's make a CPU

Introduction

In this project, we'll implement in Logisim a single-cycle processor that resembles MIPS. We'lll call the new processor and its implementation μMIPS, version 0.9.9, April 1st, 2024. Your processor will be capable of running small programs.

Start early

The deadline is close to the end of the semester. Life happens, sickness happens, so if you start early you can minimize the impact.

Do a little bit every day! 1 hour every day! 30 minutes every day! SOMETHING!

You know you will have questions, and if you decide to ask them in the last week, I may not be able to answer them all!

μMIPS Programmer's Reference Manual

μMIPS is a simplified architecture. The native word size is 16-bits. That is, instructions and data values are 16-bits wide. uMIPS data can be both unsigned, and signed using two's complement. There will be 8 registers ($ro-$r7) for general-purpose use. Important: Instruction and data memory will be separate! The instruction memory can hold up to 256 instructions, and the data memory can hold up to 256 data values.

Instructions

μMIPS has a small number of instructions: (Grouped by purpose)

In this table, "X" indicates the Subop field (see below) is not applicable and the value doesn't matter. In other words, it can be any number!

Some opcodes are not listed because these codes are reserved for future instructions.

There are some differences between uMIPS and the regular MIPS instructions. First, uMIPS is a "two-operand" instruction set. An instruction has at most two operands, including source and destination operands. In this instruction set style, one of the source operands (registers) is also the destination. For example, consider the add instruction:

add $r2, $r3

This instruction will add the contents of source registers $r2 and $r3 and put the result into destination register $r2. Register $r2 is used both as a source operand and a destination operand.

Most instructions behave like their MIPS counterparts. An important exception involves branches, which use absolute addressing to specify a target address rather than PC-relative addressing. The branches also test the conditions "equal to zero" (branch zero), "not equal to zero" (branch not zero), "less than zero" (branch negative) and "greater than zero" (branch positive).

The put instruction causes the contents of $rs to be output to a LED hexadecimal display. This instruction will assist in debugging.

The halt instruction causes the processor to stop and a stop LED to turn red.

Instruction Format

μMIPS has two instruction formats: R and I. R is used for instructions that have only registers and l is used for instructions with an immediate. The formats are:

Rs is the first source register and Rt is the second source register. Rs is the destination register.

Imm is an 8-bit immediate. The immediate is signed in addi and unsigned in addui, bn, bx, bp, bz, jal, and j. For the addition instructions with an immediate (i.e., addi and addui), the bit Subop controls whether the immediate is sign or zero extended. When Subop is 0, then Imm is zero extended to implement the addui instruction. Otherwise, Imm is sign extended to implement addi. Imm is zero extended for branches and jump (j).

In branches, jal and j, Imm specifies the target address. Both branches and jumps use absolute addressing for the target address. So, for example, if a branch is taken and Imm is Ox1a, then the target address for the branch is Ox1a.

Registers

There are eight general-purpose registers, labelled $ro to $r7. The registers are 16-bits wide.

Instruction Addresses

The instruction memory holds 256 instructions. Each instruction is 16 bits wide. An instruction address references a single instruction as a whole. Thus, an instruction address has 8 bits to specify one of 256 instructions in the memory.

Data Addresses

The data memory holds 256 16-bit data words. A data address references a single data word as a whole. Thus, a data address has 8 bits to specify one of 256 words.

Note: The notation MEMISrt & OxFF] means that only the 8-LSB of Srt are used! OxFF is a mask.

Project Requirements

Your job is to implement this architecture! Your processor will be a single cycle implementation: in one cycle, the processor will fetch an instruction and execute it.

Your implementation will need several components: 1) a program counter and fetch adder; 2) an instruction memory; 3) a register file; 4) an instruction decoder (aka the controller); 5) one or more sign extenders; 6) an arithmetic logic unit; 7) a data memory; 8) an LED hexadecimal display; and, 9) an LED to indicate the processor has halted. You'll also need muxes as appropriate. For the most part, these components are quite similar to what we've talked about in lab and lecture. You will find it helpful to consult the class slides, particularly the diagram of the MIPS processor with control signals, the controller and data path elements.

For the project, you may use any component (e.g., a 16-bit adder) from Logisim's built-in libraries. This makes the project much simpler! All other components must be implemented from scratch. Don't use or look at components that you might find on the Web or any past CS 0447 project! If you do look at this past material, this is considered cheating according to the course policy.

The usual policy about outside help applies for this assignment: It is not allowed. You may talk about how to approach the project with others, but you are not allowed to show your design or discuss specific decisions (e.g., control signal settings) with any one else other than the instructor, TAs or the CS resource center help desk.

Starting the project

Start by downloading this archive with some circuits to get you started. The archive contains 3 files where you will have to implement some parts of your CPU design:

1. RegFile. circ - In this file, you will implement your Register File. I've defined the ports you must to use, please do not modify them, or the autograder will fail.

2. ALU. circ - In this file, you will implement your ALU. I've defined the ports you must to use, please do not modify them, or the autograder will fail.

3. umips. circ-In this file, you will implement your CPU. This file will include the bulk of your CPU design.