代写Lab 2: Higher Order Logic调试SPSS

Lab 2: Higher Order Logic

Due Oct 31th, 2025, 11:59 PM

Minimum Submission Requirements

● Ensure that your lab2 folder in your Gradescope submission contains the following files (note the capitalization convention):

○ lab2_part1.dig 

○ lab2_part2.dig 

○ lab2_part3.dig 

Objective

The objective of this lab is to build a higher order logic structure and introduce an overly simple data path.

Breakdown

This assignment consists of three parts:

Part-1: Adder and Subtractor for 2’s Complement  ->complete lab2_part1.dig

Part-2: Display Decimal from 2's Complement ->complete lab2_part2.dig

Part-3: Data Path using part1 and part2 ->complete lab2_part3.dig

External Resources

Registers, Flip-Flops, and Modular Design This short video provides a very brief introduction to storage elements in digital logic. We will be utilizing their principles in lab2. If, by now, storage elements have not yet been covered in the lecture, this quick video will give you a primer on this subject. After watching this video, please go through this note on registers to ensure you have the working knowledge of storage elements needed for lab 2.

Tests

Each interface file provided contains a Test Component. These are not extensive tests. Rather, these tests are examples you may wish to follow when implementing your own tests. Your tests will not be graded, but we highly encourage you to test your circuits exhaustively to ensure proper functionality.

Specifications: Part-1

Part-1: Description

In this lab part, you will build an Adder Subtractor circuit. This circuit will implement a four bit Add_Sub. This Add_Sub will perform. an operation on 2 inputs of 4 bits each and use 1 input to identify whether the Add_Sub has to perform. addition or subtraction operation.

The Add_Sub you will be implementing consists of two 4-bit inputs (named inA and inB), one 1-bit input (named op), and one 4-bit output (named out), and one 1-bit output (named overflow). Your Add_Sub  must add inA and inB (inA+inB) if op is 0. Additionally, your add_sub must subtract inA and inB (inA-inB) if op is 1.

Part-1: User Interface  

You are provided an interface file lab2_part1.dig; start Part-1 from this file. You are not permitted to edit the content inside the dotted lines rectangle.

Figure: lab2_part1.dig Interface (Example 1)

Part-1: Example 1

In the figure above, the input values that we have selected to test are inA = {inA_3, inA_2, inA_1, inA_0} = {0, 0, 1, 1} and inB = {inB_3, inB_2, inB_1, inB_0} = {0, 1, 0, 0} and p = {1}. Therefore, considering “op” value, we must perform. (inA-inB) operation.

Explanation of output for this example:

 0011 in 2’s complement means decimal 3. 0100 in 2’s complement means decimal 4.

3-4=-1 (in decimal).

 Decimal “-1” in 2’s complement is “1111” without overflow, i.e. ut= “1111”, verflow= “0” (in binary 2’s complement).

This can be seen in the Figure above.

Figure: lab2_part1.dig Interface (Example 2)

Part-1: Example 2

In the figure above, the input values that we have selected to test are inA = {inA_3, inA_2, inA_1, inA_0} = {0, 1, 0,0} and inB = {inB_3, inB_2, inB_1, inB_0} = {0, 1, 0, 0} and p = {0}. Therefore, considering “op” value, we must perform. (inA+inB) operation.

Explanation of output for this example:

 0100 in 2’s complement means decimal 4.

4+4=8 (in decimal).

The range of 4 bit 2’s complement numbers is: {-2^(n-1) to +2^(n-1) -1} i.e. -8 to +7 in our example.

This range does not fit +8 and thus the output overflows. Thus overflow is 1 for this example output.

This can be seen in the Figure above.

When you open the lab2_part1.dig file, you will of course not see these exact values in green because that is what we used to verify your circuit correctly working by clicking on the Simulate button. On your end, you should go through all possible test cases to verify your design works. Make sure to name all the wires and input/outputs correctly so that they match the test interface names within lab2_part1.dig. You will need to do the same for part2 and part 3 as well.

Hint: Using Multiplexers will help you out a lot here.

The “Tunnel” component in Digital for Lab2

In Lab1, you might have noticed how much effort it took to draw so many inputs and wire them all over the place without unintentionally connecting them to the incorrect outputs and nodes! Turns out, Digital does provide some means to help reduce this burden.

This manifests as the Tunnel component. Go to Components->Wires->Tunnel. The symbol looks like a triangle with one vertex being a bleft dot. The idea is that instead of extending your wires physically all over your circuit drawing space by drawing them as lines, you can use tunnels as placeholders in different locations on your diagram for the same wire. These tunnels must have the same name so as to symbolize the same electrical connection.

You are provided the file playWithTunnels.dig to give you an idea of how tunnels work in Digital. Think of them as being like wormholes that can connect 2 physically separate points on your circuit diagram through the same wire connection.

Figure: playWithTunnels.dig screenshot

Note that all the Interface areas in the .dig files for part1, part2 and part3 have tunnel components in them. That means when you draw your circuit outside the interface box in these files, you will need to draw the appropriate number of tunnel wires which hook up (via wormholes!) to the provided inputs and outputs within the interface box. Make sure the tunnels have the correct wire names.

Specifications: Part-2

Part-2: Description

In this part of the lab, we will illuminate two 7-segment displays. You will need to understand 2's Complement to determine when the input 4-bit binary number corresponds to a negative or positive number. To understand how an LED display works in Digital, please refer to the playWithLED_Display.dig file provided. You should play with different input combinations to see how it influences the LED Display value. In the screenshot below, note how I was able to generate the display of “3” on the Hex display by lighting up only certain input wires to the unit.

Figure: playWithLED_Display.dig screenshot

Here is a picture of how the different segments light up to produce the different displays:

Figure: Lighting up different segments to produce display of 0-8

Note in the picture above that we showed displays only from 0-8 since in 4-bit 2s complement representation, 8 is the largest modulus value you can represent (the range of integers would be -8 to +7).

Your circuit in Part-2 must accept a 4-bit 2's complement input {in3, in2, in1, in0} where in3 is the most significant bit and in0 is the least significant bit. The outputs of your circuit must illuminate the two 7-segment displays such that they display the decimal value of the input. Since this a 4-bit 2s complement represented number, that means the range of numbers (2⁴=16) that can be shown correctly on the hex display (with sign) is [-2^4-1, +2^4-1-1] = [-8, +7]

Part-2: User Interface

You are provided an interface file lab2_part2.dig, start Part-2 from this file. You are not permitted to edit the content inside the dotted lines rectangle.

Figure: lab2_part2.dig Interface

Part-2: Example

In the figure above, the input is {in3, in2, in1, in0} = {0, 0, 1, 1} Which means the input signal in, as a bus, reads 0011. Which is the 2's complement binary representation of the value +3. Note: only the middle segment, sign_g, (it appears as sign_g on the Digital screenshot) on the left display will be illuminated, and that too ONLY for negative values. Since +3 is a positive number, it is not illuminated in the above example. All the remaining sign signals remain turned off for both positive and negative numbers.

Specifications: Part-3

Part-3: Description

In this part of the lab, you will create a data path for the Add_Sub you build in Part-1. This data path will consist of 4 registers.

In this lab, we are using the register components. Refer to playwithRegister.dig to get a good starting idea of how this component works.

You will need to address 1 register via the interface select signals to determine which 4-bit register to write the input value to. Then using the D-Flip-flops in Digital.

You will use only one Clock Input to keep the circuit synchronized. That is, with Clock=1, set up your register Clock to 1. For this lab, a manual setting of clock signal from 0 to 1 is needed. Do not create a periodic clock signal.

Part-3: User Interface

You are provided an interface file lab2_part3.dig, start Part-3 from this file. You are not permitted to edit the content inside the dotted lines rectangles.

Figure: lab2_part3.dig Interface

Part-3: Example        bcf

In this design, the user can choose out of the 4 registers where to store the 4-bit value which needs to be from (inA from part-1) and also which register to store the result of the operation (inB from part-1), using the sel_write register selection inputs. The user ensures they direct these two registers to the correct Register Selection: Read From values for inA and inB inputs values to the Add_Sub.

Clock edge is used to load the values in the registers selected. So, When you click on “Synchronizing Clock”, a positive edge of the clock is created. This makes the Register capture the data value.

In the figure above, we have written the value 3 to Register 3 and the value 4 to Register 2 and op is selected as 1 (Just like in part1 example2). Then, we read from Register 3 the value 3 to Add_Sub input A and read from Register 2 the value 4 to Add_Sub input B. Subtracting (op is 1) B from A gives Output as hexadecimal F without overflow.

Part-3: Diagram

The following diagram illustrates the high level design of this part. The black sections are provided, while the blue sections you must implement yourself.